| XS95 Pin |
Connects to... |
Description |
| 21 |
S0,BLUE0 |
These pins drive the individual segments
of the LED display (S0-S6 and DP). They also drive the color, horizontal,
and vertical sync signals for a VGA monitor. |
| 23 |
S1,BLUE1 |
| 19 |
S2,GREEN0 |
| 17 |
S3,GREEN1 |
| 18 |
S4,RED0 |
| 14 |
S5,RED1 |
| 15 |
S6,HSYNCB |
| 24 |
DP,VSYNCB |
| 9 |
CLK |
An input driven by the 12 MHz oscillator. |
| 46 |
PC_D0 |
These pins are driven by the data
output pins of the PC parallel port. Clocking signals can only be
reliably applied through pins 46 and 47 since these have additional
hysterisis circuitry. |
| 47 |
PC_D1 |
| 48 |
PC_D2 |
| 50 |
PC_D3 |
| 51 |
PC_D4 |
| 52 |
PC_D5 |
| 81 |
PC_D6 |
| 80 |
PC_D7 |
| 10 |
XTAL1 |
Pin that drives the uC clock input |
| 45 |
RST |
Pin that drives the uC reset input |
| 20 |
ALEB |
Pin that monitors the uC address latch enable |
| 13 |
PSENB |
Pin that monitors the uC program store enable |
| 6 |
P1.0 |
These pins connect to the pins of
Port 1 of the uC. Some of the pins are also connected to the status
input pins of the PC parallel port. |
| 7 |
P1.1 |
| 11 |
P1.2 |
| 5 |
P1.3 |
| 72 |
P1.4,PC_S4 |
| 71 |
P1.5,PC_S3 |
| 66 |
P1.6,PC_S5 |
| 67 |
P1.7 |
| 31 |
P3.0(RXD) |
These pins connect to the pins of
Port 3 of the uC. The uC has specialized functions for each of the
port pins indicated in parentheses. Pin 63 connects to the data
write pin of the uC and the write-enable pin of the RAM. Pin 70
connects to a status input pin of the PC parallel port. |
| 70 |
P3.1(TXD), PC_S6 |
| 69 |
P3.2(INTB0) |
| 68 |
P3.3(INTB1) |
| 26 |
P3.4(T0) |
| 33 |
P3.5(T1) |
| 63 |
P3.6(WRB), WEB |
| 32 |
P3.7(RDB) |
| 44 |
P0.0(AD0), D0 |
These pins connect to Port 0 of the
uC which is also a multiplexed address/data port. These pins also
connect to the data pins of the RAM. |
| 43 |
P0.1(AD1), D1 |
| 41 |
P0.2(AD2), D2 |
| 40 |
P0.3(AD3), D3 |
| 39 |
P0.4(AD4), D4 |
| 37 |
P0.5(AD5), D5 |
| 36 |
P0.6(AD6), D6 |
| 35 |
P0.7(AD7), D7 |
| 58 |
P2.0(A8), A8 |
These pins connect to Port 2 of the
uC which also outputs the upper address byte. These pins also connect
to the 7 upper address bits of the RAM. |
| 56 |
P2.0(A9), A9 |
| 54 |
P2.0(A10), A10 |
| 55 |
P2.0(A11), A11 |
| 53 |
P2.0(A12), A12 |
| 57 |
P2.0(A13), A13 |
| 61 |
P2.0(A14), A14 |
| 34 |
P2.0(A15) |
| 75 |
A0 |
These pins drive the 8 lower address
bits of the RAM. |
| 79 |
A1 |
| 82 |
A2 |
| 84 |
A3 |
| 1 |
A4 |
| 3 |
A5 |
| 83 |
A6 |
| 2 |
A7 |
| 62 |
OEB |
Pin that drives the RAM output enable. |
| 65 |
CEB |
Pin that drives the RAM chip enable. |
| 4 |
FREE0 |
These pins are not connected to other
devices and can be used as general purpose I/O. |
| 12 |
FREE1 |
| 25 |
FREE2 |
| 74 |
FREE3 |
| 76 |
FREE4 |
| 77 |
FREE5 |
|
